Lectures

HWs/Labs

Software

Syllabus

Links

CPE 462 - VHDL: Simulation and Synthesis - Fall'11

Required software

Active HDL - Required to simulate and verify VHDL circuits

1. ActiveHDL7.2_student_edition_installation.exe

This student version of Active HDL requires a license to run, which takes 5 minutes to get.



Xilinx ISE 7.1 - Required to load code into the FPGA boards

Note: This software is obsolete, but it is the one we have downstairs to load code into the FPGA boards. Feel free to install it at home on your windows machine.

You can:
• Install the software at home a prepare the file to be uploaded into the boards. Loading code into the boards can only be done in the lab.
• Verify your code for syntax errors.
• Visualize the synthesized circuit.
• Visualize the FPGA board layout and code statistics.
  You can't:
• Perform timing or functional simulation. That particular software (ModelSim v6) no longer has a valid license program. You can still use Modelsim v6 in the Lab computers.
  
  Install each file in sequential order:
  1. WebPACK_71_fcfull_i.exe
  2. 7_1_01i_pc.exe
  3. EDK_7_1_02i_win.exe
  4. 7_1_03i_pc.exe
  5. 7_1_04i_pc.exe
  All these files are also available here.